Paper Title: The Key Foundations and Future of DRAM - Industry Standards

Paper Abstract: DRAM is one of the core technologies required for all computing systems and most electronics in the world today. For many decades, DRAM has improved and met the needs of each generation of new technologies and workloads, while amazingly remaining drop-in compatible across suppliers. This has been accomplished through JEDEC, the global standards organization that leads the development of the industry's memory standards, including DRAM and NAND flash. With more than 3,000 volunteers representing over 300 member companies, JEDEC has been the key forum where companies have come together to decide and define the future for memory. This talk will provide an overview of the industry's key standards related to DRAM plus related implications for performance, power, and reliability, with a look back to where they've been and then forward to where things are going. It will highlight key technology initiatives that will be important to the industry and emerging trends for DRAM that will be critical to planning for the future.

Paper Author: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology
Christian Gyllenskog, , Micron Technology

Author Bio: Jonathan Hinkle is the Executive Director & Distinguished Researcher of Datacenter System Architecture in Lenovo Research, where he leads the investigation of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the CXL Memory TG standardizing CXL Memory Modules. He holds BS and MS degrees in Computer Engineering from North Carolina State University.

Author 2 Bio: Christian Gyllenskog (JILL n skog) spent years developing printer and driver solutions across the United States and Europe before joining Micron Micron’s early SSD efforts. He wrote and architected firmware and ASICs. He transitioned to Managed NAND as System Architect, where he now serves as their Ecosystems and Standards engineer, participating in JEDEC and MIPI. He served as the editorial chair for the board-approved UFS 4.0 standard. In his spare time, he is a father to seven and grandfather to one (so far) and enjoys singing, basketball and ultimate frisbee.