Paper Title: CXL Controllers for Memory Disaggregation in the Data Center

Paper Abstract: Compute Express Link (CXL) is a new cache-coherent interconnect standard for processors, memory and accelerators. This presentation will describe CXL controller architectures for memory expansion, memory pooling and acceleration. We will highlight key building blocks and explain how to optimize for metrics such as latency and bandwidth, and will describe new features for security, RAS, and data loss protection. We will also show how CXL controllers will enable new memory and accelerator modules in the data center that support higher performance and capacities than previous DIMM-based solutions.

Paper Author: Erich Haratsch, Senior Director Architecture, Marvell

Author Bio: Dr. Erich F. Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera™ SSD controllers and other memory based products. Prior to joining Marvell, Dr. Haratsch worked at Seagate and LSI, where he worked on Nytro® and SandForce® branded SSD controllers. Earlier in his career, Dr. Haratsch developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. Dr. Haratsch is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).