Paper Title: Controller Design Considerations for Samsung's CXL-SSD

Paper Abstract: PCIe-based NVMe SSDs play an important role nowadays, but it has limited its use in emerging application cases, due to higher-granular (512B/4KB) block based accesses and software involvement and high-cost IO stack based data movement between the SSDs and main memory. To meet the requirements of modern workloads that requires small-granular accesses to SSDs while avoiding paying this I/O tax, we adopt the new cache-coherent Compute Express Link (CXL) interface for next-gen SSDs, making them accessible via memory semantics, bypassing the I/O stack for finer-grained access via hardware caches, while still allowing for traditional I/O stack access for bulk transfers. In this talk, we present the controller architecture considerations for such SSDs, including device cache design and other features. We also describe our Proof-of-Concept CXL-SSD implementation. NVMe commands over CXL.io goes to the underlying SSD. CXL.mem path includes an in-device cache implementation and NVMe request and response conversion for cache misses. Finally, we will call for collaborators to work with us characterizing the device requirements as per their workload and infrastructure needs.

Paper Author: Brian Myungjune JUNG, Principal Engineer, Samsung Electronics Semiconductor

Author Bio: Brian Myungjune Jung is principal engineer of Samsung Electronics Memory, leading the development next generation projects such as SmartSSD and CXL-SSD. He led Ethernet SSD firmware development project, and did host-device performance engineering for NVMe SSDs and SAS SSDs. Before joining in Samsung Electronics Memory, he did storage systems research and system virtualization research in Samsung Advanced Institute of Technology. He received his B.S. and M.S. in Electronics Engineering from Kyungpook National University.