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3:10-4:15 PM
AIAP-302-2: Storage for AI Part 2 (Artificial Intelligence Applications Track)
Paper Title: Solving AI Workload's Storage Problem with CXL and Tiered Memory

Paper Abstract: Modern data center AI workloads are no longer fitting into Accelerator memory or even main memory. Production models have already reached TBs in size and are fast growing, leading to the use of tiered memory for these workloads across Accelerator memory, main memory and NAND flash SSDs. However, purely software-based solutions can get quite complicated and/or result in additional unnecessary data movements that will lower performance. This talk will show how Samsung's new cache-coherent Compute Express Link (CXL) SSD can solve the problem by providing fine-grained access via memory semantics and device side hardware caches, bypassing the I/O stack, while still allowing for traditional I/O stack access for bulk transfers. Our approach enables fine-grained application-controlled data movement across the different tiers, and reduces the AI software stack complexity. We will demonstrate the benefits through end-to-end evaluation of the memory-dominated DLRM recommendation model inference using a Proof-of-Concept CXL SSD device implementation. We will also welcome others in the development of the AI ecosystem to support hardware-software co-designed tiering.

Paper Author: Marie Nguyen, Sr. Research Engineer, Samsung Semiconductor

Author Bio: Dr. Marie Nguyen is a Sr Research Engineer in the Systems Technology Group, Samsung Memory Solution Lab (https://samsungmsl.com/) in San Jose, California. Her areas of research include storage solutions for machine learning, FPGA runtime/overlay using partial reconfiguration (PR), and FPGA acceleration of real-time vision applications. She got her PhD from Carnegie Mellon University in 2020.