Paper Title: Near-Memory-Computing- The Hidden Winner?

Paper Abstract: World's academia and industry is looking at in-memory-computing for inference of CNNs. It shall overcome the Von-Neumann bottleneck and enable AI for edge computing with ultra-low power and high TOPS/W. Which is true for cell array level can change drastically when we look at system level where routing power for input and output feature maps are not negligible anymore. We investigated an NMC architecture and several IMC architecture alternatives including single level and multi-level cells as well as different ADC and placement options. We present energy efficiency, area and speed trade-offs between the different architectures.

Paper Author: Marko Noack, Member of Technical Staff, Ferroelectric Memory

Author Bio: Marko Noack received the M.Sc. degree in electrical engineering from Technische Universität Dresden, Germany in 2011. He was working on VLSI implementations of neuromorphic circuits at the Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Technische Universität Dresden. In 2016 he co-founded the start-up company Ferroelectric Memory GmbH, where he currently is Member of Technical Staff and project leader. He works on non-volatile memory circuit designs based on FeFET devices.