Paper Title: Upgrading Verification Infrastructure for NVMe 2.0

Paper Abstract: NVMe 2.0 introduces various new features and updates to existing features for new command sets. These features allow innovations in storage space but also make the functional verification of NVMe controller more challenging. e.g. ZNS allows SSD and host to collaborate on data placement and opens possibilities for features like computational storage. This increases the scope of the verification test plans to validate command operations and data transfers to multiple command sets and to various regions, memory score boarding across power cycles, and keeping compliance with older devices. These challenges require the solution to be agile and adaptable. We will discuss the important characteristics of verification solution from planning to closure. We will see how by using common APIs, different kinds of access to commands and data structures using UVM features like callbacks and analysis components will make the solution highly adaptable for new features and support various transports keeping the high-level stimulus similar. We will see a case study on how the above techniques helped our NVMe QVIP customer verify a new feature Key per IO and achieve lesser time to market.

Paper Author: Prashant Dixit, LMCS, Mentor Graphics

Author Bio: Prashant Dixit is currently leading the Storage Verification IPs team at Siemens EDA, which deals with the development and testing of NVMe and NVMe over Fabrics testing solutions. Previously, he worked at Mentor Graphics and Samsung in the design and verification of IPs and SoC of networking and in the storage domain. He has completed a Master of Engineering in Microelectronics from BITS Pilani in 2006 and a Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.