Paper Title: An Alternative for NAND Flash Innovation

Paper Abstract: The NAND flash industry relies on a variety of methods for improving economics, performance, space, and power. Yet, the progress from one generation to the next is not enough to keep pace with changing requirements. Architectural innovations offer alternatives for advancing NAND flash characteristics. Examples include reducing the size of memory dies, shortening the length of bit lines, decreasing the number of page buffers, and increasing the number of planes. The resulting NAND flash designs would require no cell or array structure changes and no process or technology changes, so manufacturing costs would remain similar.

Paper Author: Andy Hsu, Founder & CEO, NEO Semiconductor

Author Bio: Andy is the Founder & CEO of NEO Semiconductor. He has 25 years of experience in the semiconductor industry. Before founding the company, he led the R&D and Engineering teams of a startup company for 16 years and developed more than 60 products in NOR flash, EEPROM, and NVSRAM. He is an inventor of 100+ granted US patents in non-volatile memory. He wrote a thesis about Artificial Neural Networks in graduate school. He earned an MS in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) and a BS from the National Cheng-Kung University in Taiwan.