Paper Title: CXL3.0: New Features for Increased Scale & Optimized Resource Utilization

Paper Abstract: Compute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics. It uses high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices, and is designed to deliver an open standard that accelerates the next-generation data center performance. Industry use cases are driving the need for higher bandwidth, including high-performance accelerators, system memory, Smart NICs, and leading-edge networking. Interconnects are needed that can optimize system level flows among those components with advanced switching, efficient P2P, and fine-grained resource sharing across multiple domains. This presentation will provide a quick overview of the CXL 2.0 specification and new ECNS to enhance performance, reliability, software interface, and testability while offering design simplification. It will then introduce the new features in the CXL 3.0 specification.

Paper Author: Ishwar Agarwal, CXL Consortium MWG Co-Chair, CXL Consortium

Author Bio: Ishwar Agarwal is a Principal Hardware Engineer at Microsoft. Ishwar is also the CXL Consortium Technical Task Force Co-Chair.