Paper Title: Power & Latency Analysis of the Memory Tiering Pyramid

Paper Abstract: The Memory Tiering Pyramid has frequently been used to explain and justify technological shifts in memory architecture over the years. It conveys an idealistic model of graceful progression through memory hierarchy with increasing distance, latency, capacity and persistence. Yet, behind this enticing pyramid is a complex array of architectural nuances that bear little resemblance to the beauty of the Pyramid. This presentation will break down the memory pyramid into its constituent parts, and will redraw them with a more accurate representation of today's computing architectures. It will then propose a future Power and Latency friendly Computing Architecture that will faithfully replicate the ideal Memory Tiering Pyramid. The proposed solution will show how both OMI and CXL will play important roles in this Shared Memory Centric, Distributed Computing World.

Paper Author: Allan Cantle, CEO, Nallasway

Author Bio: Allan Cantle is CEO of Nallasway, consulting on Heterogeneous, High Performance Computing Solutions. He is currently contracting with the OpenCAPI Consortium as the Technical Director and Board Advisor. He also volunteers as the Technical Lead for the OCP HPC SubProject. Previously, Allan was the founder of Nallatech, which, during his 25 year tenure, became widely known as a pioneer in FPGA Accelerated Computing. Before founding Nallatech; Allan was an Electronics Systems Engineer at BAE systems, developing real-time heterogeneous high-performance computers. He holds a BEng degree in Electrical and Electronics Engineering from the University of Plymouth and an MSc in Corporate Leadership.