Paper Title: High Performance Computing with Hybrid Bonding 3D Interconnect

Paper Abstract: AI and machine learning applications are driving the performance of next generation computing hardware. To meet the increasing performance, data centers need low latency, significant memory bandwidth with lower power consumption. Today, High Bandwidth Memory (HBM) stacks are used with high performance CPUs or GPUs to address this need. Various interconnect technologies and integration methods are used in CoWoS, EMIB or Foveros etc 2.5D/3D integrated solutions to enable higher bandwidth. These solutions use microbump or Cu-pillar interconnect technologies which have fundamental limitations in interconnect pitch scaling. Hybrid bonding based 2.5D /3DIC solutions can eliminate the bottleneck of chip-to-chip connectivity by adding high density Cu-Cu 3D interconnects. The memory logic I/O can be increased by up to 1000 times. The scalability of the hybrid bonding interconnect offers massive parallel processing with chiplet architectures that enable performance enhancements without the need to move to a smaller transistor node. The higher yield with smaller chiplet die and the ability to select optimized functions with fast productization timeline offers a lower cost of ownership.

Paper Author: Laura Mirkarimi, VP of Engineering; 3D Portfolio and Bonding Technology, Adeia - Xperi

Author Bio: Laura Mirkarimi is VP of Engineering, 3D Portfolio and Bonding Technology at Adeia, the newly launched brand for the IP Licensing business of Xperi Holding Corporation, San Jose, California. She received a PhD in Materials Science at Northwestern U. Dr. Mirkarimi leads the 3D team at Xperi. Prior to joining Xperi, she developed electronic devices including ferroelectric memory, transparent conductors and photonic crystal resonators at Hewlett Packard Laboratories for 12 years. She holds more than 50 patents and 45 publications.