Paper Title: Challenges in Gen5 CXL Testing

Paper Abstract: Compute Express Link (CXL) is a new open interconnect standard for enabling coherent memory access between high-bandwidth devices. It is built on the PCI Express physical and electrical interface with protocols in 3 areas: I/O, memory, and cache coherence. This talk will provide an in-depth review of issues faced when creating a CXL 2.0 development and test platform using a CXL 1.1 host. To aid in device development and debugging, a comparison of CXL features supported by previous and future versions of the Linux kernel is included. Usage and modification of industry standard tools that support CXL.mem testing is also addressed, along with an examination of possible problems that may arise when testing CXL.cache and coherency-related issues with CXL 3.0.

Paper Author: Justin Treon, Applications Engineer, Advantest

Author Bio: Justin Treon is a Factory Application Engineer at Advantest, where he focuses on SSD protocol testing for SATA/SAS/PCIe/NVMe. Justin's SSD and memory-related experience includes SSD security, firmware, performance analysis, and testing and configuring memory interfaces such as DRAM, SPI, traditional NOR, and NAND flash. Justin has a total of 17 years experiences at Advantest, Micron, and Intel. He is also a specialist in embedded Linux, RTOS and scheduler-based systems with work experience in device drivers, board bring up, JTAG and UART debugging for ARM based systems, performance optimization, and memory reduction. He earned a BS in computer engineering from California State University Sacramento and has written three publications.