Paper Title: Reducing Solid-State Drive Read Latency by Optimizing Read-Retry

Paper Abstract: 3D NAND flash memory with advanced multi-level cell techniques provides high storage density but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly increase the read latency of an SSD by introducing multiple retry steps. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash chips, This talk will discuss new opportunities to reduce the read-retry latency, including two new techniques: 1) Pipelined Read-Retry (PR-R) and 2) Adaptive Read-Retry (AR-R). PR-R reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR-R shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation that our proposal improves SSD response time by up to 31.5% (17% on average) over a state-of-the-art baseline with only small changes to the SSD controller.

Paper Author: Jisung Park, Senior Researcher and Leturer, ETH Zürich

Author Bio: Jisung Park is Senior Research and Lecturer in SAFARI Research Group at ETH Zürich. He has worked on the efficient design of NAND flash-based storage systems to improve performance, reliability, lifetime, and security/privacy. He earned his bachelor's degree in Computer Science and Ph.D. degree in Electrical Engineering and Computer Science at Seoul National University in 2011 and 2019, respectively.