Paper Title: PCIe 6.0 Specification: An Interconnect for the Next Generation of Storage

Paper Abstract: For the past three decades, PCI-SIG has delivered a succession of industry-leading PCI Express (PCIe) specifications that remain ahead of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments, including data centers, artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and Storage applications. In early 2022, PCI-SIG released the PCIe 6.0 specification to members. The latest evolution of PCI Express technology doubles the data rate of the PCIe 5.0 specification to 64 GT/s (up to 256 GB/s for a x16 configuration) via innovative new features like Pulse Amplitude Modulation with 4 levels (PAM4) signaling, low-latency Forward Error Correction (FEC) and Flit-based encoding. This presentation will cover the benefits PCIe 6.0 technology offers for diverse market segments, including AI/ML, HPC, and Storage, as well as updates on the adoption of PCIe 4.0 technology in solid state drives (SSDs) and the PCIe 5.0 Compliance Program. Attendees will also learn about the potential use cases for PCIe 6.0 technology and its relationship with other protocols.

Paper Author: Al Yanes, STSM, PCI-SIG

Author Bio: Al Yanes has served as president of the PCI-SIG since 2003 and chairman since 2006 and is a Senior Technical Staff Member working in the IBM Storage Group. He has 38 years of experience working with in the I/O industry. Yanes holds 25 patents for PCI™ and other I/O technologies. Yanes holds a B.S. in computer engineering from Rensselaer Polytechnic Institute.