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9:45-10:50 AM
AIAP-301-2: Neural Networks (Artificial Intelligence Applications Track)
Paper Title: Accuracy of Analog Neural Network Inference Accelerators

Paper Abstract: A major hurdle in developing high performance and power efficient edge AI inference hardware can be overcome by using a memory approach that performs computation in on-chip flash cells. However, computation using flash memory arrays has proven to be challenging primarily due to the power and area overhead imposed by the peripheral circuitry, and due to the non-ideal properties of memory devices that play a key role for the synapse implementation. This talk will analyze how the overall system accuracy is impacted by various parameters like flash cell bit capability, cell current sigma, cell read noise, programming accuracy, ADC resolution, cell retention, etc., and will attempt to provide an understanding of the various technology and implementation challenges. We will also demonstrate that even with the various non-idealities present in NVM-based IMC architecture (cell + periphery), we can attain within 2% accuracy of a fully digital implementation for real world ML architectures while achieving 10-50x increase in energy efficiency. We will also show Silicon and Simulation data demonstrating near digital accuracy on medium and large benchmarking networks.

Paper Author: Vineet Agrawal, Sr. Director, Infineon Technologies LLC.

Author Bio: Vineet Agrawal received his B.Tech and M.Tech degrees from Indian Institute of Technology (IIT) Madras, in 2006. He is currently a Senior Design Director at Infineon Technologies, where he works on developing ultra-low power ML accelerators and differentiated memory products. Vineet has over 18 years of experience in advanced memory design and technology development and holds over15 US patents. His current research interests include the design and architecture of NVM based compute-in-memory accelerators for edge AI applications.