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3:30-4:35 PM
SARC-202-1: CXL Attached Memory (System Architectures Track)
Paper Title: Solving Memory Bottlenecks in Compute Systems with CXL-Based Memory Controllers

Paper Abstract: Compute Express Link delivers breakthrough memory performance required by cutting edge Internet of Things (IoT), Artificial Intelligence (AI) and Machine Learning (ML) applications. The addition of the CXL memory interface enables compute accelerators to scale core count, per core frequency, and device capacity in a cost effective way. By leveraging existing PCIe infrastructure, CXL instantly becomes broadly available to deliver both memory expansion and increased memory bandwidth far beyond the capabilities of traditional parallel Double Data Rate (DDR) interfaces. This talk will provide an overview of CXL memory technology, critical design, latency, and thermal considerations, and an outlook on industry adoption of this emerging technology.

Paper Author: Tim Symons, Associate Technical Fellow, Microchip Technology

Author Bio: