Paper Title: Recent DRAM Technology Overview: Trends & Challenges

Paper Abstract: When it comes to DRAM cell scaling, cell capacitance will be the most important keyword. DRAM cell capacitance continued to decrease due to the device scaling, and D1z and D1a (or D1α) cell capacitance is already showing lower than 7 fF/cell. The high-k dielectric layer thickness was shrunken to 7 or 6 nm, and the process integration already changed from cylindrical capacitor to quasi-cylindrical or one-sided capacitor structure. Now, DDR5 DRAM, GDDR6, and HBM2E products are common on market. Samsung EUV lithography has been applied onto Samsung D1z LPDDR5 DRAM chips. Regarding the DRAM D/R trend from major players, 10 or 9 nm nodes may well be the last one for the 6F2 DRAM cell. DRAM foundries are eager to extend this by developing more innovative technologies, materials, and methodologies such as gate work-function engineering, KHMG, sensing margin and speed improvement, row-hammer scaling, higher NA EUV tools, etc. Recent DRAM technology details, trends, and challenges will also be discussed.

Paper Author: Jeongdong Choe, Senior Technical Fellow, TechInsights

Author Bio: Dr. Jeongdong Choe is the Senior Technical Fellow and Subject Matter Expert at TechInsights, and he provides semiconductor process and device technology details, insights, roadmaps, trends, markets, predictions, and consulting/IP services on DRAM, 3D NAND, NOR, and embedded/emerging memory devices to leading Memory and Storage manufacturers, semiconductor materials and equipment vendors, institutes, and IP related agents. Jeongdong’s extensive background in DRAM, NAND, NOR, Package, and Embedded/Emerging Memory Devices including MRAM, PCRAM, XPoint, ReRAM, and FeRAM is built on 30+ years of hands-on industry experience serving as SME and consulting engineer of Memory & Logic analysis team at TechInsights, Director at Samsung Semiconductor, Principal Engineer at Hynix, and Senior Process Engineer at LG Semicon (old Goldstar Electronics). Jeongdong is a Memory icon, and he is frequently invited as a speaker at international conferences as an expert on memory technology details, trends, comparison insights, and process/device challenges. He holds a master’s degree in Materials Engineering from Yonsei University and a Ph.D. in Semiconductor Systems Engineering from Sungkyunkwan University. He is an author/co-author of 100+ semiconductor-related patents.