Paper Title: Improving hard-decoding ECC with irregular LDPC codes free of error floor

Paper Abstract: The error correction requirement for the latest and upcoming NAND memories is more and more demanding in terms of reliability and throughput. From 3D-TLC to 3D-QLC and to PLC NAND, the need for stronger error correction is solved by considering controllers using LDPC codes with more overhead. In this presentation, we show that by using irregular LDPC codes, the ECC performance of hard-decision LDPC decoders can be greatly improved, up to 25% gain, even for codes with small overhead. By doing so, we push further the request of soft information from multiple reads of the Flash, and therefore reduce the global latency of the controller and extend the life of the device. Irregular LDPC codes decoded with classical decoders have typically a high error floor, which prevents them to be used in storage applications, where the target UBER can be as low as 1e-17. We propose improvements of FAID decoders that completely eliminates the error floor of irregular LDPC codes, without degrading the ECC capability. Moreover, the improved ECC comes at a small hardware cost, which makes FAID-decoded irregular LDPC codes a suitable solution for next generation controllers.

Paper Author: David Declercq, CTO, CodeLucida

Author Bio: David Declercq is the co-founder and CTO of Codelucida Inc. He was previously full professor at the ENSEA in Cergy-Pontoise, France, from 2001 to 2017. He is a senior member of the IEEE, and a widely renowned researcher in the area of LDPC code and decoder design. He published more than 150 papers in the area, and holds 11 patents. Several of his contributions towards LDPC code and decoder design have been employed by industry as well as adopted in several standards. He is especially recognized for his pioneering works on non-binary LDPC code and decoder designs, and his recent developments of LDPC decoders without error floors.