Paper Title: Generalized Integrated Interleaved Codes for Hyper-Speed Memories

Paper Abstract: Generalized integrated interleaved (GII) codes can nest BCH sub-codewords to form more powerful BCH codewords. In most cases, the decoding only needs to be carried out on the short individual sub-words and hence can achieve very high speed with low complexity. On the other hand, more errors are correctable by the nested decoding process. Therefore, GII codes are among the best error-correcting codes for memories requiring hyper-speed decoding and excellent correction capability. This talk presents our recent results on GII decoder design. Algorithmic reformulations have been developed to eliminate the clock frequency bottleneck, enable reconfigurable Chien search, increase hardware utilization efficiency, and address miscorrections in the case of short codes. Our GII decoder can easily achieve more than 50GByte/s throughput with low complexity.

Paper Author: Xinmiao Zhang, Associate Professor, Ohio State University (ECE Department)

Author Bio: Xinmiao Zhang received her Ph.D. degree from the University of Minnesota in 2005. She joined The Ohio State University as an Associate Professor in 2017. Prior to that, she was a Senior Technologist at Western Digital. Her research spans the areas of digital storage and communications, VLSI architecture design, security, and cryptography. She is currently the VP-Technical Activities of the IEEE Circuits and Systems Society and the Chair of the Data Storage Technical Committee of the IEEE Communications Society. She is also a member of the IEEE CASCOM, VSA, and DISPS technical committees. She has served on the committees of many conferences, including ISCAS, SiPS, ICC, GLOBECOM, and NVMW. She is a recipient of the NSF CAREER Award in 2009.