Paper Title: Overcoming NAND Limitations with a Layered SSD FW Architecture

Paper Abstract: The industry continues to innovate around different types of SSDs that optimize usage models to overcome limitations in NAND architecture. This talk will introduce a layered firmware architecture which supports multiple SSD FTL optimizations with different I/O command sets: conventional SSD, ZNS, K-V, Open Channel and Computational Storage SSDs. Since more I/O command sets are incorporated into the NVMe 2.0 specification, the NVMe controller chip vendor faces the challenge of employing one single flexible HW/FW architecture to productize multiple SSD variants to accelerate time-to-market while providing higher performance and predictable QoS. This talk will share our learning on designing the layered firmware architecture in SMI Gen5 NVMe controller to overcome the challenges.

Paper Author: David Wang, Director, Enterprise SSD Firmware, Silicon Motion

Author Bio: David has been technical director at Silicon Motion since 2020, leading the FW architecture of Next Gen enterprise SSD/ZNS SSD as well as CSD. From 2006-2019, he worked at PMC-Sierra/Microsemi/Microchip, focusing on high performance firmware architecture design of multiple SAS/NVMe/PCIe enterprise storage chips including SAS Expanders, SAS HBA, PCIe Storage Switch, NVMe controller.