Paper Title: Design Challenges and Tradeoffs with QLC-Based ZNS SSDs

Paper Abstract: This talk address architecting ZNS SSDs that use QLC NAND: how to overcome issues and deal with the various design tradeoffs, with the hope that our design experience can be an inspiration to the community. The following challenges will be addressed: o The ZNS specification allows for an open design space in terms of active/open zone count and zone size. However, from the perspective of the SSD controller, these don't come for free due to resource and performance implications. Thus, is is critical to carefully weigh various tradeoffs, and to establish reasonable boundaries in the design space. o QLC is chosen for good random read performance, acceptable sequential write performance, and lower cost. However, the 16-16 programming sequence places a significant demand on write data buffering, and thus poses a difficult engineering problem given the limited resources available in SSD controllers. o Furthermore, QLC is notorious for its retention. Slow charge loss causes the read voltage Vth shift, which is very sensitive for QLC. FW must expend effort to track Vth at the granularity of NAND pages, and this effort will enlarge due to the possibility of many open blocks in the system.

Paper Author: Guanying Wu, Principal Engineer, Silicon Motion

Author Bio: Since 2021, Guanying has been a principal engineer at Silicon Motion, focusing on next-generation SSD architecture. From 2013 to 2021, he worked in enterprise SSD firmware development at Micron/Seagate/LSI. In 2013, he received his Ph.D. with a focus on SSD performance and reliability studies.