Paper Title: Maximizing Performance of Enterprise QLC-Based SSDs with Flash Processing Units

Paper Abstract: As QLC is playing a more significant role in SSD applications, we are seeing new challenges in enterprise and data center applications. Consistency, predictable latency, higher IOPs and larger Total Byte Writes (TBW) are the key requirements in these more advanced applications. An FPU (Flash Process Unit) concept will be discussed which will provide a novel architecture demonstrating how to achieve these needs while highlighting QLC's benefits. Higher IOPS and larger TBW can be covered larger capacity from more flash channels and QLC dies. QLC's higher RBER also impacts performance because error recovery reliability concerns increase read latency. The use of FPUs will ensure that error recovery is avoided in advance, and will result in a nearly constant latency even under mixed read/write behavior to allow for a better user experience with enterprise level QLC SSDs.

Paper Author: Jeff Yang, Principal Engineer, Silicon Motion

Author Bio: Jeff Yang is a Principle Engineer of Algorithm & Technology team at Silicon Motion. Prior to Silicon Motion, he has worked with Realtek Inc. on several WiFi projects. He holds He holds a M.S.E.E. from National Taiwan University, Taiwan. His research in error correcting codes addresses effective encoding/decoding algorithms and VLSI architectures. His current research interests include error correcting codes system for NAND flash applications.