Paper Title: Future of Wafer-to-Wafer Bonding to Overcome NVM Density Limitations

Paper Abstract: Wafer to wafer hybrid bonding has been introduced in new generation memories to eliminate several NAND manufacturing challenges. This is a novel 3D (three-dimensional) NAND flash architecture where the NAND array wafer is joined to the logic wafer through direct hybrid bonding. This design continues Moore's law in the third dimension. Direct hybrid bonding process is complex and requires exceptionally fine pitch 3D interconnect. The bonding of individual wafers delivers high performing NAND memory while maximizing memory density. Wafer to wafer hybrid bonded NAND chips is compared to CMOS under Array (CuA) 3D NAND and conventional 3D NAND memories to reveal density and cost benefits of the novel design. This presentation compares YMTC's 128 layer 3D NAND using wafer to wafer bonding to Micron's CMOS under Array 3D NAND and Samsung's 3D NAND using Periphery on the side all produced on 12-inch wafers. The effects of wafer to wafer bonding will show the impact the technology has on density, productivity and cost. Benefits of wafer-to-wafer bonding are attractive and could be widely adopted in the future to to overcome some challenges faced in current manufacturing processes.

Paper Author: Belinda Langelihme Dube, Engineer, Consultant

Author Bio: Belinda Dube serves as a Technology & Cost Analyst at System Plus Consulting, part of Yole Développement. Belinda’s core expertise is memory technology, especially DRAM and 3D NAND flash memory. At the same time, she also investigates IC technologies as well as advanced packaging. Her mission and goal are to develop reverse engineering & costing reports. She also works on custom projects, where she works closely with the laboratory team to set up significant physical & chemical analyses of innovative memory chips Belinda holds a master’s degree in Instrumentation & Nanotechnology Engineering from INSA (France).