Wednesday, August 9th
|SARC-203-2: UCIe and Chiplets (System Architectures Track)|
|Organizer: Jim Pappas, Director, Technology Initiatives, Intel|
Paper Title: UCIe Manageability and Software
Paper Abstract: Founded in 2022, the UCIe Consortium is an industry Consortium dedicated to advancing UCIe (Universal Chiplet Interconnect Express) technology an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The UCIe 1.0 specification provides provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing. The specification leverages the established PCI Express® (PCI-SIG®) and Compute Express Link (CXL) industry standards. It will enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoC. This presentation will share a deep dive into the UCIe Manageability and Software.
Paper Author: Jerome Glisse, Assistant Account Executive, Nereus Worldwide
Author Bio: Jerome Glisse serves as the UCIe Consortium Manageability/Security Work Group Co-Chair and is a software engineer at Google.