Wednesday, August 9th
|SARC-203-2: UCIe and Chiplets (System Architectures Track)|
|Organizer: Jim Pappas, Director, Technology Initiatives, Intel|
Paper Title: Explore the usage models for UCIe technology
Paper Abstract: UCIe (Universal Chiplet Interconnect Express) addresses customer requests for a more customizable, package-level integration combining best-in-class die-to-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem. UCIe supports two broad usage models. The first is a package level integration to deliver power-efficient and cost-effective performance. The second is to provide off-package connectivity using different types of media (e.g., optical, electrical cable, mmWave) using UCIe Retimers to transport the underlying protocols (e.g., PCIe, CXL) at the rack or even the pod level to enable resource pooling and sharing, and even message passing using load-store semantics beyond the node level to the rack/ pod level to derive better power-efficient and cost-effective performance at the edge and data centers. In this presentation, attendees will gain insight into the UCIe 1.0 specification and explore the usage models UCIe enables.
Paper Author: Manual Mota, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel
Author Bio: Manuel Mota is a senior staff product marketing manager in the Synopsys Solutions Group. He has extensive experience in the semiconductor industry, with expertise in high-speed IO protocols, analog and mixed-signal designs, and wireless IP. Manuel has a Ph.D. in electronics from Instituto Superior Tecnico.