Wednesday, August 9th
3:30-4:35 PM
FMAR-203-1: QLC High Density Storage (Flash Memory Architectures Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Title: Achieving Near-SLC Performance for QLC & PLC NAND Flash

Paper Abstract: Generational advances in 3D NAND flash memory increase capacity but decrease performance. The technology industry effectively mitigated this tradeoff until the shift to the current QLC (4 bits/cell) and emerging PLC (5 bits/cell) generations. Their sustained write speed has dropped below HDD speed (160 Mb/s). This session explores an innovative approach involving architectural and design changes to enable sustained writing, reading, and verifying data for QLC and PLC flash at SLC-like (1 bit/cell) speeds.

Paper Author: Ray Tsay, Co-Founder & VP of Engineering, NEO Semiconductor

Author Bio: Ray Tsay has over 30 years of experience in the semiconductor industry. Prior to NEO, he worked at many companies including Integrated Silicon Solution (ISSI), ICT, and EG&G Reticon. He led engineering teams for testing, product, and manufacturing. He has broad experience in various products such as CCD, CPLD, SRAM, EEPROM, EPROM, and flash memory. He holds a MS degree in Electrical and Computer Engineering from Arizona State University, a MS in Chemical and Material Engineering from the University of Iowa, and a BS in Chemical Engineering from National Central University in Taiwan.