Wednesday, August 9th
|SARC-203-2: UCIe and Chiplets (System Architectures Track)|
|Organizer: Jim Pappas, Director, Technology Initiatives, Intel|
Paper Title: UCIe Protocol Overview
Paper Abstract: The presentation will cover an overview of the different layers of UCIe stack, covering the functionality split between the different layers. Link protocol will be covered including main-band and sideband transfers, Link training, as well as a summary of supported Protocol mappings (PCIe/CXL/Streaming) and the corresponding Flit formats.
Paper Author: Swadesh Choudhary, Silicon Architecture Engineer, Intel
Author Bio: Swadesh is an IO Architect and Tech Lead in the IO Technology and Standards (IOTS) group at Intel. He has over a decade’s experience implementing and architecting interconnect technologies covering PCIe, CXL, multi-chip interconnects, coherency and fabric architecture. He has actively participated in PCIe SIG and CXL Consortium. He serves as a co-chair for the Protocol Working Group in the UCIe Consortium. Swadesh holds over 30 patents and has earned a M.S.E.E degree from Stanford University.