Paper Title: Die Stacking with Hybrid Bond Interconnect for DRAM

Paper Abstract: As the industry continues to increase the bandwidth and density of memory in processors, an improved interconnect that scales beyond the micro-bump is needed. Hybrid bonding offers a scalable interconnect to meet the shrinking pitch demands for memory processor interfaces. Additionally, the interconnect provides a lower capacitance and inductance over Cu micro-bump for enhanced signal performance. We have prepared 4, 8 and 12 die stacks of test structures to evaluate the assembly parameters and feasibility of stacking multi-die with the hybrid bond interconnect to TSV. We share results for enhanced metrology to obtain improved yield in the hybrid interconnect at the wafer level. We report on all Cu hybrid bond interconnect performance as a function of die edge, stacking layer and share environmental stress and reliability performance of test vehicles prepared with a thermal budget of 200oC. Cu grain engineering experiments show the possibility of further reducing the thermal budget in high volume manufacturing.

Paper Author: Laura Mirkarimi, SVP- Engineering, Adeia

Author Bio: Laura leads the engineering team at Adeia and is currently focused on developing advanced packaging technologies including hybrid bonding, heterogeneous integration, and thermal management. In 2019, she and her team demonstrated DBI Ultra, a manufacturing worthy process, for die to wafer hybrid bonding with all die handling on tape frame. Since then the team has worked with many customers and partners to bring up the DBI process within their supply chain. She obtained a BS in Ceramic Engineering at Penn State and a PhD in Materials Science at Northwestern industry and holds ~90 patents.