Wednesday, August 9th
3:30-4:35 PM
FMAR-203-1: QLC High Density Storage (Flash Memory Architectures Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Title: QLC: Understanding Its Limitations and Its Critical Areas

Paper Abstract: As we progress in the flash technology to produce denser memory architectures, we need to understand the current limitations of QLC NAND. To further strengthen and support our venture into even denser NAND, we need to analyze QLC NAND at its core to understand its limits and criticalities in these key areas: QLC programmed data and charge loss/degradations wrt: Ranges of retention period varying up to max life of NAND Ranges of PE cycles varying up to max life of NAND Number of NAND WL layers With each variation, study: Voltage Shift in probability states of various programmed states of QLC. To check for the extent of data correction possible with various methods (listed) and their effectiveness : ECC Parity only Read Voltage Prediction ECC Parity + Read Voltage Prediction To check the best and worst TTR (Time to Read) metrics associated with different programmed states. Repeat the whole experiment at varying level of temperatures and understand the extent of impact of temperature on QLC's error tolerance and retention.

Paper Author: Akash Shaw, Staff Engineer, Samsung Electronics

Author Bio: Team Akash Shaw, staff engineer, Samsung semiconductor India research(SSIR) Phanindrakumar Yakkaladevi, staff engineer, Samsung semiconductor India research(SSIR) We are working together in Memory solution team, our role is to verification and qualification of SSD products across protocols(SATA, NVMe etc). Educational background: Akash Shaw - completed B.Tech in NIT warangal, India Phanindrakumar Yakkaldevi - completed B.Tech in JNTU Kakinada, India