Wednesday, August 9th
8:30-9:35 AM
SARC-201-1: CXL Tiering (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: Software Defined Memory with CXL

Paper Abstract: Compute Express Link (CXL), an open-standard interconnect protocol, overcomes architectural limitations by efficiently expanding memory capacity and bandwidth. CXL provides various cost effective and power efficient solution with memory expansion. The Device HW and SW stack on host can be tuned to deliver high performance and low latency solutions . The presentation talks about device capabilities and how SW stack can leverage these to provide better system level performance by tuning existing kernel and applications stack. Insight into various real time use cases and performance advantage with heterogenous interleave and SW tiering.

Paper Author: Ravi Kiran Gummaluri, Director , CXL System Architecture, Micron Technology

Author Bio: Ravi Kiran has over 20+ years of experience in leading System Architecture and Embedded system design for various organizations . Currently he is working for Micron in leading System Architecture for CXL based Micron products . Earlier to Micron, Ravi was working with Xilinx in leading CXL , CCIX and PCIe reference design . He has presented in various international conferences(FMS, SDC, SC) on coherent interconnects and its use cases . He has Master's degree in Embedded system Design .