Wednesday, August 9th
3:30-4:35 PM
SARC-203-1: CXL Memory Challenges (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: Challenges of memory diversity in CXL ecosystem

Paper Abstract: Compute Express Link (CXL) has enabled the possibility of memory customization. Diverse memory media can now be glued to a larger compute system. Commodity processors of our time are increasingly adopting expensive, high-bandwidth and low-power HBMs, while relegating less expensive and slower memories to distant CXL fabric locations, few NUMA hops away. Making multiple disparate memories work with equally diverse compute elements like CPU, GPU, TPU and accelerators, brings about a new set of challenges and opportunities. This presentation outlines a few hardware and software challenges, along with potential solutions to enable a composable server comprising of diverse compute and memory elements.

Paper Author: Sanketh Srinivas, Tech staff Applications Eng, Microchip Technology

Author Bio: Sanketh Srinivas is a product manager for CXL Memory Controllers in the Data Center Solutions business unit at Microchip. Sanketh has contributed to product development for 13+years. Sanketh has a Master's degree in Electrical Engineering from the New York University.