Wednesday, August 9th
9:45-10:50 AM
SARC-202-1: CXL RAS (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: RAS in CXL Memory Controllers

Paper Abstract: Compute Express Link (CXL) is a high-speed, low-latency interconnect technology designed to accelerate next-generation data center workloads. To maintain the dependable operation; Reliability, Availability, and Serviceability (RAS) are important considerations in data center applications. The CXL standard defines multiple RAS features and capabilities for the vendors to innovate with their own solutions and still interoperate with each other. Some of the RAS capabilities defined by the CXL consortium include Error Detection and Correction, End-to-End protection, Fault Isolation and Diagnostics, Data Poisoning, Viral and Hot Plug and Play. Overall, CXL RAS capabilities help ensure the robustness of systems using CXL technology, providing administrators with the tools they need to diagnose and correct problems quickly and efficiently.

Paper Author: Ranjit Gupte, Technical Staff Applications Engineer, DCS, Microchip Technology

Author Bio: Ranjit Gupte is a Technical Staff Applications Engineer for next gen CXL and PCIe products in the Data Center Storage Solutions Business Unit (DCS) of Microchip Technology. Ranjit has been in the Semiconductor industry for more than 20 years with 10+ years of experience Enterprise Storage Industry. He holds a Master’s Degree in Electrical Engineering from University of Rhode Island.