Wednesday, August 9th
8:30-9:35 AM
SARC-201-1: CXL Tiering (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: CXL 3.x - Advancing Data Center Architectures with Memory Tiering

Paper Abstract: This session provides a forward-looking view of Data Center Architectures that includes additional tiers of memory compared to contemporary implementations. A review of system level impacts, including a latency analysis, both average and tail impacts of different tiers of memory, including hot tiers, cold tiers, and the impacts of capabilities such as compression.

Paper Author: Danny Moore, Senior Manager, Product Managment and Strategy, Rambus

Author Bio: Danny Moore is a Senior Manager of CXL Product Management and Strategy. Danny has over 25 years of experience defining, building, and testing system-on-chip and interconnect devices for a multitude of platforms including AI/ML, HPC, storage and automotive. He is an active contributing member of the CXL consortium and most recently has been focused on CXL 3.x and its associated task force.