Wednesday, August 9th
9:45-10:50 AM
SARC-202-1: CXL RAS (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: Challenges and Opportunities for RAS & ECC in CXL 3.x based Systems:

Paper Abstract: The CXL specification defines innovative technologies that enable great system design flexibility and novel use cases. However, these new system architectures also introduce challenges and opportunities in the areas of RAS (Reliability, Availability, and Serviceability) and ECC. This session will describe these new challenges and the solutions available in the CXL 3.x Specification. The presentation will also cover the importance of minimizing Silent Data Corruption (SDC) in the datacenter.

Paper Author: Larrie Carr, VP Engineering, Rambus

Author Bio: Larrie Carr is the VP of Engineering at the newly formed Interconnect SoC business unit at Rambus Inc. He is leading the development and architecture of Rambus’ new product initiatives which are focused on enabling memory connectivity, expansion, pooling, and switching using CXL technology. Before Rambus, Larrie was a Technical Fellow at Microchip Technology responsible for technical strategy and architectural guidance for Microchip's broad portfolio of datacenter solutions, including serial memory controllers, SSD controllers, RAID solutions, PCIe switches, SAS expanders, and other initiatives not publicly announced. During that time, Microchip provided significant contributions to the CXL 2.0 standard in the areas of switching and fabric management under Larrie’s supervision. While at Microsemi Corporation (later acquired by Microchip), Larrie led internal innovation and external technical engagements related to OpenCAPI, Gen-Z, Compute Express Link (CXL) and RISC-V within the Microsemi CTO organization. Among other outcomes, these engagements resulted in the development and eventual productization of the industry’s first in-production serial memory controller ASIC (OMI to DDR4). Prior to Microsemi, Larrie led product architecture for PMC-Sierra’s enterprise storage business unit from inception to an industry leadership position. During that tenure he established PMC-Sierra as a technology leader in the area of storage connectivity, security, reliability, availability, and serviceability – concepts that extend well into the tiered memory architecture that the CXL standard will enable. He also served as a private consultant conceiving many of the industry's first-generation non-volatile memory solutions. Larrie is an active board member of the CXL Consortium as well as a former board member and officer of the Gen-Z consortium. He is a registered Professional Engineer and earned a bachelor’s degree and master’s degree in electronic engineering from Simon Fraser University in Vancouver, Canada.