Paper Title: UCIe™: Building an Open Chiplet Ecosystem

Paper Abstract: Last year, leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers announced the formation of the UCIe Consortium to establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The UCIe open industry standard interconnect offers high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets. It addresses the projected growing demands of compute, memory, storage, and connectivity across the entire compute continuum spanning cloud, edge, enterprise, 5G, automotive, high-performance computing, and hand-held segments. This presentation will introduce the features of the UCIe 1.0 specification, share an update on the progress of the UCIe specification, and explore the innovations in the ecosystem that UCIe will enable.

Paper Author: Debendra Das Sharma, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel

Author Bio: Dr. Debendra Das Sharma is a Senior Fellow at Intel Corporation. He is an expert in IO subsystem and interface architecture, delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), coherency, multichip package interconnect, SoC, and rack scale architecture. He is the Chairman of the UCIe Consortium, Technical Task Force Co-chair of CXL™ Consortium, and a board member of PCI-SIG.