Paper Title: PCIe® 7.0 Specification: 128 GT/s bandwidth for Future Data-Intensive Markets

Paper Abstract: For the past three decades, PCI-SIG® has delivered a succession of industry-leading PCI Express® (PCIe®) specifications that remain ahead of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in storage applications and diverse market segments.PCI-SIG recently announced the PCIe 7.0 specification is targeted for release in 2025. The feature goals of the upcoming specification include doubling the data rate of the PCIe 6.0 specification to 128 GT/s and up to 512 GB/s bi-directionally via x16 configuration, PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding, improved power efficiency and maintaining backwards compatibility with all previous generations of PCIe technology.This session will update attendees on the feature goals of the PCIe 7.0 specification and the benefits for diverse applications, including 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets like Hyperscale Data Centers, High-Performance Computing (HPC) and Military/Aerospace. Attendees will also receive updates on the PCIe 6.0 specification market adoption and the PCIe 5.0 Compliance Program.

Paper Author: Al Yanes, STSM, PCI-SIG

Author Bio: Al Yanes has served as president of the PCI-SIG since 2003 and chairman since 2006 and is a Distinguished Engineer for IBM in the Systems & Technology Division. He has 26 years of experience working with ASIC design in the I/O industry. Yanes holds 25 patents for PCI™ and other I/O technologies. Yanes is a PCI Express® technology expert for the IBM Rochester office and he is involved in I/O design for IBM's Server products. Yanes holds a B.S. in computer engineering from Rensselaer Polytechnic Institute.