Wednesday, August 9th
8:30-9:35 AM
SARC-201-1: CXL Tiering (System Architectures Track)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Title: CXL 2.0 Composable Memory Implementations

Paper Abstract: This presentation discusses an external CXL switch implementation for composable memory. The 256 lanes CXL switch will be used for host and CXL memory connections to form a composable memory cluster. The topics will be the system topology (1 layer CXL switch, 2 layer CXL switch), the usage case (scale up memory, memory pooling, and memory sharing), fabric management API/ GUI (what API is used by users), performance results (the latency in different architecture), and implementation experience sharing.

Paper Author: Brian Pan, General Manager, H3 Platform

Author Bio: I am Brian Pan, CEO and founder of H3 Platform. Brian has long experience in developing the PCIe composable solution including GPU, NVMe SSD, and network cards. Since the CXL fabric is based on PCIe fabric, he is working on the composable CXL memory solution by using the CXL switch. Besides, Brian has rich experience working with tier 1 cloud service providers and data centers to design composable solutions.