Wednesday, August 9th
8:30-9:35 AM
OMEM-201-1: Emerging Memory and Flash Innovations (Other Memory Technologies Track)
Organizer + Instructor: Bill Gervasi, Principal Systems Architect, Discobolus Designs

Paper Title: The Great Convergence; How CXL and UCIe Challenge the Memory Wall

Paper Abstract: The industry seems to finally be agreeing on a coherent fabric for large systems interconnect. At the macro level, CXL creates a unified space in which heterogeneous processing power can enjoy heterogeneous memory and storage resources. At the micro level, UCIe extends the fabric with a consistent chip to chip interface. This talk explores the evolution of systems architectures to understand how we got here, including lessons from the past. The Memory Wall, or the inability of DRAM to keep pace with system demand, is explored and memory on CXL/UCIe examined in detail to see how it impacts the Wall.

Paper Author: Bill Gervasi, Principal Systems Architect, Discobolus Designs

Author Bio: Bill Gervasi is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.