Paper Title: Introducing ULTRARAM: A high-performance, ultra-efficient, non-volatile memory

Paper Abstract: The $167bn (2021) memory market is dominated (96%) by DRAM and flash. They have complementary roles in the memory hierarchy that exploit their strengths; low switching energy and speed for DRAM and non-volatility and low cost for flash. Yet, their disadvantages, refresh and destructive read for DRAM and slow, high-voltage program/erase and poor endurance for flash, have stimulated research into emerging memories that could combine their advantages, without their disadvantages. To date emerging memory has not outperformed DRAM or competed with the low cost of flash, and occupies <1% of the memory market. This has led to the perception that a non-volatile memory that can match the performance of DRAM is unachievable. We will introduce Flash Memory Summit to ULTRARAM, a compound-semiconductor, floating-gate memory where the oxide barrier between the floating gate and the channel is replaced by a triple-barrier resonant tunnelling structure. This eliminates flash’s deficiencies, delivering a non-volatile memory that has the potential to out-perform DRAM, with non-destructive read, low program/erase voltages, high endurance, high switching speeds and ultra-low switching energies.

Paper Author: Manus Hayne, Chief Technology Officer, Quinas Technology

Author Bio: Prof Hayne is co-founder and Chief Technical Officer of Quinas Technology, recently spun out from Lancaster University to commercialise ULTRARAM memory technology. He is Deputy Head of the Physics Department at Lancaster, Director of Research and Industrial Engagement and Impact Champion. He is co-author on >100 articles and (co-)inventor on several (pending) patents, including on ULTRARAM. He gained a BSc in Physics with Electronics from Southampton University and a PhD in Physics from Exeter, and spent 10 years working in Paris and Leuven before being appointed at Lancaster.