Wednesday, August 9th
3:30-4:35 PM
DRAM-203-1: DRAM Technology (DRAM Track)
Paper Title: DRAM Technology and Process 2023: Current and Future

Paper Abstract: DRAM cell scaling down to the 14 nm design rule (D/R) has already been productized by major DRAM players such as Samsung, Micron, and SK Hynix. They’re developing n+1 (12~13 nm) and n+2 (11 nm or beyond) so-called D1b (D1β), D1c (D1γ), and D1d (D1δ) or even D0a generation now, which means DRAM cell D/R might be able to further scale down to single digit nm with EUVL adoption for DRAM cell/core patterning. Major DRAM players have applied EUVL masks on DRAM and will expand it for the next generation. Current 6F2 cell architecture with 1T+1C will be moving over to 4F2 or 3D DRAM in a 7~8 nm D/R DRAM generation due to scaling limitations, which will be D0b or D0c. HKMG DRAM process has been adopted on Graphic DRAM and advanced DDR5 DRAM products by Samsung and Micron, although etching and high-k engineering are different for each. Current and future DRAM technology and process challenges will be discussed.

Paper Author: JEONGDONG CHOE, Senior Technical Fellow, TechInsights

Author Bio: Dr. Jeongdong Choe is the Senior Technical Fellow and Subject Matter Expert at TechInsights. Dr. Choe provides semiconductor process and device technology details, insights, roadmaps, trends, markets, predictions, and consulting/IP services on DRAM, 3D NAND, NOR, and embedded/emerging memory devices to leading Memory and Storage manufacturers, semiconductor materials and equipment vendors, institutes, and IP related agents. Dr. Choe’s extensive background in DRAM, NAND, NOR, Package, and Embedded/Emerging Memory Devices including MRAM, PCRAM, XPoint, ReRAM, and FeRAM is built on 30+ years of hands-on industry experience serving as a subject matter expert and consulting engineer of Memory & Logic analysis team at TechInsights, Director at Samsung Semiconductor, Principal Engineer at Hynix, and Senior Process Engineer at LG Semicon (old Goldstar Electronics). Dr. Choe is a Memory icon, and he is frequently invited as a speaker at international conferences as an expert on memory technology details, trends, comparison insights, and process/device challenges. He holds a master’s degree in Materials Engineering from Yonsei University and a Ph.D. in Semiconductor Systems Engineering from Sungkyunkwan University. He is an author/co-author of 100+ semiconductor-related patents.