Wednesday, August 9th
9:45-10:50 AM
OMEM-202-1: Life Beyond Flash (Other Memory Technologies Track)
Paper Title: Stacked Dynamic Flash Memory (DFM) for a High-Density Memory

Paper Abstract: This presentation proposes a double stacked ‘Dynamic Flash Memory (DFM)’ for realizing a high-density memory. As for the DFM scalability, the 3D DFM has a variety of structures, such as the vertical SGT DFM, and lateral FinFET or stacked GAA DFM [1-3]. In the case of the SGT DFM, the cell size would be about 4F2. DFM is a capacitorless cell, so that the cost for the capacitor fabrication should be reduced. Even though the pillar pitch of the SGT DFM were 50 nm, the equivalent DFM cell size should be much smaller than that of the conventional DRAM cell. Furthermore, the DFM needs no special materials, which means that DFM can be fabricated with the conventional Si process unlike emerging memories, such as ReRAM, FeRAM, and MRAM. References [1] K. Sakui and N. Harada, “Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT),” in Proc. IEEE IMW, pp.72-75, May 2021. [2] K. Sakui, M. Kakumu, and Nozomu Harada, “Perfect Read Non-Destructive Dynamic Flash Memory (DFM),” 2022 Flash Memory Summit, Aug. 2022. [3] K. Sakui, M. Kakumu and N. Harada, “Dynamic Flash Memory with Fast Block Refresh,” in NVMTS (Non-Volatile Memory Technology Symposium), pp.15-16, Dec. 8, 2022.

Paper Author: Koji Sakui, Executive Technical Manager, Unisantis Electronics Singapore Pte Ltd.

Author Bio: In 1981, he joined the Toshiba Research and Development Center, Toshiba Corporation, where he was engaged in the circuit design of DRAM’s. Since 1990 he has been engaged in the development of high- density NAND Flash memories. He managed Flash Memory Design Department of SoC R & D Center to develop 90nm, 70nm, and 55nm NAND Flash memory design. He moved to Sony Corporation in 2004 and served as a General Manager of Memory System Department of System LSI Business Division, Semiconductor Business Group. In 2007, he moved to NAND Products Group, Intel Corporation, where he was a Research Scientist. In 2009, he became a Visiting Professor of Tohoku University. In 2010, he joined Micron as Sr. Architect and Technologist – Memory Innovations, where he has 87 US granted patents on the 3D NAND. In 2017, he became a Principal Scientist of Honda Research Institute Japan. In 2020 he has become an Executive Technical Manager of Unisantis Electronics Singapore Pte Ltd. Dr. Sakui is a member of the IEEE Electron Device Society and served a Technical Program Committee for the IEEE NVSMW (Non-Volatile Semiconductor Memory Workshop), currently the IEEE IMW (International Memory Workshop) from 1998 to 2012. In 2012 he became an IEEE Fellow, with the accompanying citation: “for the contribution to NAND flash memories.” He holds 177 US patents granted and published over 30 technical papers. He received Kanagawa Governor Patent Award in 1997 and Kanto District Patent Award in 2005.