Thursday, November 12th
8:35-10:05
Session A-9: Computational Storage Increases System Throughput and Scalability (Computational Storage Track)
Organizer: JB Baker, Senior Director of Product Management, ScaleFlux

Paper Title: Using Computational Storage to Handle Big Data

Paper Abstract: Machine learning, deep learning and analytics all require enormous amounts of data. Moving all that data to servers for processing is becoming increasingly burdensome and time-consuming. Sure, processing cores and GPUs are more powerful than ever, but network bandwidth and DRAM cost limit how big a dataset can be analyzed. As such, off-loading tasks to storage can reduce network traffic and optimize the work done by expensive processors. Computational storage allows data to reside close to processing power, thus allowing processing tasks to be in-line with data accesses. NVMe SSDs and external storage appliances can act as many distributed processing engines that can perform compression, sorting, searching, and profiling. Inference engines placed in the storage can even do pre-processing for machine learning. Ultimately, much of the application could be distributed to all the ASICs, FPGAs, and small processing units in NVMe SSDs. Computational storage examples already in use illustrate ways to overcome these issues, and there are still other promising directions to explore for the future.

Paper Author: Andy Walls, Fellow/CTO/Chief Architect, Flash Storage, IBM

Author Bio: Andy Walls is Chief Architect and CTO for IBM's Flash Systems Division, and is widely recognized as an expert in storage and flash memory. He is an IBM Fellow, IBM's most prestigious honor. A 35-year storage industry veteran, Andy is a pioneer in enabling flash memory in the enterprise, including enabling TLC and QLC flash in the enterprise. He has developed an infrastructure for servers and storage which achieves the highest performance while still providing the endurance and availability that the enterprise and data center require. He was responsible for the Texas Memory Systems acquisition, and has since defined the architecture for all FlashSystem products including the very popular FlashSystem 840 and 900. He is currently defining next-generation products that can be used in traditional SAN environments and clouds, and also by emerging workloads. Andy has designed ASICs, PCBs, firmware stacks, and systems. Known as an innovator, he has filed over 100 patents. Andy earned a BSEE from UC Santa Barbara.