Thursday, November 12th
1:45-3:15
Session A-11: Flash Controllers for Application Acceleration (PRO) (Controllers Track)
Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Paper Title: Machine Learning for Bad Page Prediction in Flash

Paper Abstract: Flash memory is prone to failures as the number of program-erase cycles increases, resulting in an increase in the bit error rate. Once the bit error count exceeds a certain threshold, error correction engines are either incapable of continuing to correct the errors efficiently or they may fail entirely. This leads to an interest in learning the behavior of the error count increase and obtaining an ability to make failure predictions. This talk will tackle this problem using a machine learning approach, although standard ML techniques may not work well with the particular data in hand. This is because the error counts are collected from actual flash memory and one can expect to see more pages with a lower error count than pages with a higher error count. This feature of the data-set leads to a formulation of our goal in terms of a classification problem with significant class imbalance in the underlying data. The talk will also cover various classification methods that address such class imbalance, including cost-sensitive boosting techniques, bagging procedures, ensemble support vector machines and cost-sensitive neural networks.

Paper Author: Navya Sree Prem, Student/ SSD Architecture Engineer II, UCSD/ Seagate

Author Bio: Navya Sree Prem was pursuing Master of Science in Electrical and Computer Engineering at University of California, San Diego during the course of this work. The work was a part of the master's thesis advised by Professor Paul H. Siegel. She is currently working for Seagate with the SSD architecture team.