Thursday, November 12th
1:45-3:15
Session A-11: Flash Controllers for Application Acceleration (PRO) (Controllers Track)
Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Paper Title: Achieving latency and reliability targets with QLC in enterprise controllers

Paper Abstract: The 3D QLC NAND flash memory characteristics exhibit remarkable challenges in terms of latency and reliability resulting in an unassertive adoption in the enterprise storage market. We demonstrate that through an innovative controller design and novel flash management algorithms these challenges can be effectively mitigated. Emphasis is given to read voltage calibration and data placement alternatives and their critical role in achieving low error-rates and low read latency performance. We present experimental results that demonstrate the improvements from various read voltage calibration and data placement schemes and discuss the specific trade-offs in accuracy and controller complexity of such schemes. Our findings demonstrate that implementing these techniques in a QLC controller not only achieves TLC-like performance but can even outperform traditional TLC controller designs which are widespread in enterprise storage systems today.

Paper Author: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Author Bio: Roman Pletka is a research staff member and master inventor for cloud storage, data, and AI systems at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He is a frequent speaker at international conferences, has published over 20 articles and obtained more than 90 patents in managing non-volatile memories, security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over 15 years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).