Paper Title: SPI NAND Host-Side Error Correction

Paper Abstract: Memory-intensive applications such as high-end consumer products, networking, and industrial systems are putting cost pressures on designers that drive engineers to find new avenues for reducing system cost while improving performance. An essential technology for maintaining reliability and extending memory longevity in SPI NAND flash is found in error code correction (ECC). With the goal of achieving greater efficiency in these applications for SPI NAND flash-based systems, developers use architectures in which ECC is implemented in the host MCU, instead of those with integrated ECC. This presentation will address the differences between integrated and host-based ECC, and detail each approach’s impact on system performance, reliability, and ultimately cost.

Paper Author: Salman Rashid, Sr Marketing Director, Macronix

Author Bio: Salman Rashid is the senior director of marketing at Macronix America, a leader in code-storage non-volatile memories. Salman is responsible for product positioning and business development in the Americas, focusing on applications that require high reliability such as automotive, datacenter and medical. He has been in the storage industry for 20 years working at companies like Silicon Storage Technology (acquired by Microchip) and Spansion (acquired by Cypress/Infineon). Prior to entering the semiconductor industry, Salman worked in developer relations at Apple, helping seed new technologies to hardware and software developers. He is a frequent participant in various conferences, including several past Flash Memory Summits and also manages Macronix's participation at CES. He earned his bachelor of science degree in Information Systems from the University of Oklahoma.