Thursday, November 12th
8:35-10:05
Session A-9: Computational Storage Increases System Throughput and Scalability (Computational Storage Track)
Organizer: JB Baker, Senior Director of Product Management, ScaleFlux

Paper Title: Real-World Deployments

Paper Abstract: Machine learning, deep learning and analytics all require enormous amounts of data. Moving all that data to servers for processing is becoming increasingly burdensome and time-consuming. Sure, processing cores and GPUs are more powerful than ever, but network bandwidth and DRAM cost limit how big a dataset can be analyzed. As such, off-loading tasks to storage can reduce network traffic and optimize the work done by expensive processors. Computational storage allows data to reside close to processing power, thus allowing processing tasks to be in-line with data accesses. NVMe SSDs and external storage appliances can act as many distributed processing engines that can perform compression, sorting, searching, and profiling. Inference engines placed in the storage can even do pre-processing for machine learning. Ultimately, much of the application could be distributed to all the ASICs, FPGAs, and small processing units in NVMe SSDs. Computational storage examples already in use illustrate ways to overcome these issues, and there are still other promising directions to explore for the future.

Paper Author: Stephen Bates, CTO, Eideticom

Author Bio: Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.