Paper Title: Hyperdimensional Computing & Cognitive Memory of the Pattern Kind

Paper Abstract: Hyperdimensional computing (HDC) is an emerging computing framework that draws inspiration from attributes of the mammalian neo-cortex such as hyperdimensionality, fully distributed holographic representation, and (pseudo) randomness. When employed for machine learning tasks such as learning and classification, HDC involves manipulation and comparison of large patterns within hetero-associative persistent memory. Moreover, a key attribute of HDC is its robustness to the imperfections associated with the computational substrates on which it is implemented. It is therefore particularly amenable to emerging non-von Neumann paradigms such as in-memory computing, where the physical attributes of nanoscale emerging memory devices can be exploited to perform associative pattern computations in place. Preliminary scaled versions of this under the radar memory type have proved their value in use cases that stretch from the ultra-low power edge upward through Cloud implementations.

Paper Author: Gil Russell, CTO, WebFeet Research

Author Bio: Gil Russell is now involved in Computational Memory Research as he continues exploring the next generation semiconductor based hardware for accelerating Search, Sort, Cluster and Hierarchical Affinity Propagation for Cloud, Enterprise and Edge/IoTs Pattern Computing (solving the memory qualitative search problem with a massively parallel yet low power algorithmic approach). His research has taken a path through In-Memory Computing, Near Data Processing Acceleration for Predictive Analytics and then on to Distributed Hyperdimensional effected solutions. An off shoot of this research is the development of the Pattern Memory architecture specification to facilitate real time Hyperdimensional Computing for In-Memory Machine Learning, Inference and Artificial General Intelligence applications. He has initiated and managed numerous new product definition activities - participating as a team member of new product development engineering groups; technical lead of new product introductions; technical interface and liaison to external partnerships at Infineon Technologies, Siemens Microelectronics, NEC and Samsung Semiconductor. He conceived and developed the Reduced Latency DRAM [RLDRAM] Architecture in 1998 which has become the defacto standard for high performance High Bandwidth Memory (HBM) for AI and communications processors. Mr. Russell's semiconductor memory experience includes existing product support; new product development; initial customer contact and product concept engagement; baseline specification development; projectization; directing & tracking follow through; collateral development and support; troubleshooting (all levels); and product introduction through manufacturing release. His industry standards work include Synchronous DRAM; DDR1; DDR2; DDR3; DDR4; LPDRAM; RDIMM; LRDIMM; RLDRAM; SLDRAM; JEDEC BoD - JC42/16 Chairs and M11 Memory Steering Committee.