Timezone isn't accessible, please provide the correct parameters
eventFeedUrl=http://realintelligence.com/customers/expos/00Do0000000aAt2/FMS_xmlcreator/a0J1J00001H0ji2_specific-event-list.xml
trackCategory=Session
eventID=a0J1J00001H0ji2
timezone=
duration=PTH
, NaNth
8:30-10:50 AM
CHNA-101-1: Flash Growth & Opportunity in China (China Track)
Paper Title: The Future of RRAM: From Embedded Application to In Memory Computing and Beyond

Paper Abstract: RESISTIVE random access memory (RRAM) is very attractive for dense storage in embedded applications because of its good scalability and complementary metal-oxide-semiconductor (CMOS) compatibility. The unique property of RRAM enables area efficient and low-power combined logic and memory, applying RRAM to embedded nonvolatile memory (NVM) and computing-in-memory (CIM) applications are significantly reducing the latency and energy consumption in artificial intelligence (AI) edge devices. At the same time, due to some physical random features of RRAM, it can be used to design TRNG and PUF, which increases the security and privacy of the system. However, continued transistor scaling increases random variation, and wire routing resistance and capacitance, it degrades RRAM chip performance and results in design difficulties. Smart and adaptive write and read circuits are proposed to fix yield and power consumption issues, also we elaborate novel circuits/architectures based on RRAM to accomplish computing in memory, hardware security etc., benefits of computing architecture based on RRAM in comparison with other alternative technologies will be discussed.

Paper Author: Jianguo Yang, Associate Professor, Institute of Microelectronics of the Chinese Academy of Sciences

Author Bio: Jianguo Yang is an associate professor in the Key Laboratory of Microelectronics Devices and Integrated Technology at Institute of Microelectronics of the Chinese Academy of Sciences. His research interests include circuit designs for volatile and nonvolatile memory, hardware security, memory-centric computing and memristor logics. He has authored or co-authored several technical papers such as JSSC, Symposium on VLSI, TVLSI, ISCAS, ESSCIRC & ESSDERC etc.. Some of his recognitions include two Best Paper Awards from the IEEE International Conference on ASIC on high performance memory circuit design. He has participated in several large industry and government sponsored center-level projects. He earned a PhD from Fudan University (Shanghai, China).