Paper Title: Physical Chip-ID based Encryption and Security in SSD Controller

Paper Abstract: To collect huge quantity of data, huge numbers of widely-deployed IoT devices play a central role. The most significant security problem in BigData is, accordingly, whether we can trust deployed IoT devices outside of our control. The concern is that adversaries' machines may provide false information in the IoT network. The Proof-of-Trust of deployed IoT devices having flash memories is an indispensable security criterion for the 5G/IoT services. We demonstrate, using a FPGA kit, a method to provide a set of secret and public key from physical randomness related to a flash controller. First, we retrieve a distribution pattern of irreversible fail bits from a mass-produced chip used in flash controllers. The retrieved distribution pattern is physically random and specific to each chip (chip physical randomness). Next, by combining a challenge (passcode) and the chip's physical randomness, a set of secret and public keys are generated using the FPGA kit. Since this pattern is irreversible, the keys are stable to temperature change even without additional modules and determined by a combination of the chip's physical randomness and passcode input to an IoT device.

Paper Author: Hiroshi Watanabe, Professor, National Chiao Tung University

Author Bio: Hiroshi Watanabe, PhD, is a full professor and teaching flash memory and semiconductor technologies in dept. of Electrical & Computer Engineering, National Chiao Tung University, Taiwan. He has published many journal & conference papers and invented 145 granted patents all over the world (including 62 US granted). Until 2010, he had worked for Toshiba’s Headquarter RD Center and been engaged in the reliability study of several electron devices including NAND Flash. He received PhD in theoretical physics in 1994 from U. Tsukuba, Japan. He is a Senior Member of IEEE.