Paper Title: Overcoming Challenges in MRAM High-Volume Manufacturing

Paper Abstract: There is a growing interest in using Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) technology for SRAM replacement beyond 5nm node as it demonstrates high performance, excellent scalability, and low power consumption for next-generation embedded memory to extend from eFlash. The 1T-1MTJ STT-MRAM bit cell is more compact and scalable than the 6T SRAM cell. However, MRAM remains challenging for high volume manufacturing (HVM) because of the process complexity: deposition and growth of up to 50 layers with sub-Ångstrom precision required to optimize device performance. The presentation will provide a review of systematic process optimization of magnetic tunnel junction (MTJ) stack design, patterning unit-processes, and fabrication hardware and capabilities to address these challenges. The most recent device data will be discussed to demonstrate hardware, process, and material stack development that meets MTJ performance requirements.

Paper Author: Kevin Moraes, Vice President, Applied Materials

Author Bio: Kevin Moraes is vice president of Global Product Management in the Metal Deposition and Packaging (MDP) division at Applied Materials, Inc. He is responsible for metals and PVD deposition, as well as the product roadmaps for ALD/CVD and PVD and metal deposition applications. Dr. Moraes has published 15 papers and has been awarded 5 patents. Dr. Moraes received his Ph.D. in materials science and engineering from Rensselaer Polytechnic Institute, and a bachelor degree in chemical engineering from Annamalai University. He also holds an MBA from the Hass School of Business at the University of California, Berkeley.