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8:30-10:50 AM
CTRL-201-1: Controllers and Flash Technology, Part 1 - Hardware and Algorithms (Controllers Track)
Paper Title: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives

Paper Abstract: We design a lightweight I/O request scheduler to enforce fairness across applications in modern multi-queue SSDs (MQ-SSDs) with new host--interface protocols such as NVMe. These new protocols remove the OS software stack that was used by older protocols to control how and when I/O requests were dispatched, but this eliminates existing I/O fairness control mechanisms that were implemented within the OS. We experimentally analyze real enterprise MQ-SSDs, and find that the lack of fairness control mechanisms results in four major sources of interference among applications accessing the same SSD. We propose the Flash-Level INterference-aware scheduler (FLIN). FLIN protects against all four sources of interference, through the use of a novel three-stage scheduling algorithm that can be implemented completely in the SSD controller firmware. Compared to a state-of-the-art I/O scheduler, FLIN improves the fairness and performance of a wide range of enterprise and datacenter storage workloads, with an average improvement of 70% and 47%, respectively.

Paper Author: Saugata Ghose, Special Faculty Systems Scientist, Carnegie Mellon University

Author Bio: Saugata Ghose is a Systems Scientist in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research spans a wide range of topics in the area of memory and storage systems, including data-driven architectures, NAND flash reliability, processing-in-memory, GPU memories, and emerging memory technologies. He has published several highly-cited works in top-tier conference venues and journals (including multiple works on experimentally characterizing error sources in both 2D and 3D NAND flash memories), has won a best paper award for his work on NAND flash memory forensics, and has written book chapters on NAND flash memory reliability and on processing-in-memory. He serves as Flash Memory Summit's Academic Coordinator. He earned his MS and PhD in computer engineering from Cornell University, and dual BS degrees from the State University of New York Binghamton.